?2005 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN5069 Rev. 1.1.5
14
In the case of aluminum and polymer based capacitors,
the output capacitance is typically higher than normally
required to meet these requirements. While selecting the
ceramic capacitors for the output; although lower ESR
can be achieved easily, higher capacitance values are
required to meet the V
OUT(MIN)
restrictions during a load
transient. From the stability point of view, the zero
caused by the ESR of the output capacitor plays an
important role in the stability of the converter.
Output Capacitor Selection (LDO)
For stable operation, the minimum capacitance of 100礔
with ESR around 100m?is recommended. For other val-
ues, contact the factory.
Power MOSFET Selection (PWM)
The FAN5069 is capable of driving N-Channel MOSFETs
as circuit switch elements. For better performance,
MOSFET selection must address these key parameters:
?SPAN class="pst FAN5069EMTCX_2464147_3"> The maximum Drain-to-Source Voltage (V
DS
) should
be at least 25% higher than worst-case input voltage.
?SPAN class="pst FAN5069EMTCX_2464147_3"> The MOSFETs should have low Q
G
, Q
GD,
and Q
GS.
?SPAN class="pst FAN5069EMTCX_2464147_3"> The R
DS_ON
of the MOSFETs should be as low as possible.
In typical applications for a buck converter, the duty
cycles are lower than 20%. To optimize the selection of
MOSFETs for both the high-side and low-side, follow dif-
ferent selection criteria. Select the high-side MOSFET to
minimize the switching losses and the low-side MOSFET
to minimize the conduction losses due to the channel
and the body diode losses. Note that the gate drive
losses also affect the temperature rise on the controller.
For loss calculation, refer to Fairchild's Application Note
AN-6005 and the associated spreadsheet.
High-Side Losses
Losses in the MOSFET can be understood by following
the switching interval of the MOSFET in Figure 22. MOS-
FET gate drive equivalent circuit is shown in Figure 23.
Figure 22. Switching Losses and Q
G
Figure 23. Drive Equivalent Circuit
The upper graph in Figure 22 represents Drain-to-
Source Voltage (V
DS
) and Drain Current (I
D
) waveforms.
The lower graph details Gate-to-Source Voltage (V
GS
)
vs. time with a constant current charging the gate. The x-
axis is representative of Gate Charge (Q
G
). C
ISS
= C
GD
+ C
GS
and it controls t1, t2, and t4 timing. C
GD
receives
the current from the gate driver during t3 (as V
DS
is fall-
ing). Obtain the gate charge (Q
G
) parameters shown on
the lower graph from the MOSFET datasheets.
Assuming switching losses are about the same for both
the rising edge and falling edge, Q1's switching losses
occur during the shaded time when the MOSFET has
voltage across it and current through it.
Losses are given by (EQ. 10), (EQ. 11), and (EQ. 12):
P
UPPER
= P
SW
+ P
COND
(EQ. 10)
(EQ. 11)
(EQ. 12)
where P
UPPER
is the upper MOSFET's total losses and
P
SW
and P
COND
are the switching and conduction losses
for a given MOSFET. R
DS(ON)
is at the maximum junction
temperature (T
J
) and t
S
is the switching period (rise or
fall time) and equals t2+t3 (Figure 22.).
The driver's impedance and C
ISS
determine t2 while t3's
period is controlled by the driver's impedance and Q
GD
.
Since most of t
S
occurs when V
GS
= V
SP,
assume a con-
stant current for the driver to simplify the calculation of t
S
using the following equation:
(EQ. 13)
Most MOSFET vendors specify Q
GD
and Q
GS
. Q
G(SW)
can be determined as:
Q
G(SW)
= Q
GD
+ Q
GS
Q
TH
where Q
TH
is the gate
charge required to reach the MOSFET threshold (V
TH
).
Note that for the high-side MOSFET, V
DS
equals V
IN
,
which can be as high as 20V in a typical portable appli-
cation. Include the power delivered to the MOSFET's
(P
GATE
) in calculating the power dissipation required for
the FAN5069.
V
SP
t1
t2
t3
4.5V
t4
t5
G(SW)
V
DS
I
D
Q
GS
Q
GD
V
TH
V
GS
C
ISS
C
GD
C
ISS
Q
C
GD
R
D
G
R
GATE
C
GS
HDRV
5V
SW
VIN
P
SW
V
DS
I
L
?/DIV>
2
--------- ----------- - 2 t
s
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
F
SW
=
P
COND
V
OUT
V
IN
--- ---------- -
?/DIV>
?/DIV>
?/DIV>
?/DIV>
I
OUT
2
R
DS ON
( )
?/DIV>
?/DIV>
=
t
s
Q
G SW
( )
I
Driver
--- ---------------- -
Q
G SW
( )
V
CC
V
SP
R
Driver
R
Gate
+
- ----------------- ----------------- -----
?/DIV>
?/DIV>
?/DIV>
?/DIV>
--------------- ----------------- ------------- -
H
=
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